1 www.pericom.com pi6lc48c51 rev . a 08/27/15 pi6lc48c51 pin confguration block diagram description te pi6lc48c51 is a single lvcmos output synthesizer opti - mized to generate ethernet, sonet/sdh, or sata reference clock frequencies and is a member of pericoms hiflex family of high performance clock solutions. using a mhz crystal with diferent frequencies, it can generate various output frequencies with very low phase jitter. it is ideal for ethernet, sonet/sdh, and sata/sas interfaces in all kind of systems. features ? ? single lvcmos output ? ? supports 70mhz - 170mhz output frequency range ? ? rms phase jitter @ 155.52mhz, (1.875mhz C 20mhz): 0.2ps (typical) ? ? full 3.3v or 2.5v supply modes ? ? industrial ambient operating temperature ? ? available in lead-free package: 8-tssop applications ? ? networking systems ? ? sonet / sdh systems ? ? server / storage systems pfd vco /32 osc xtal_out xtal_in /n clk oe fs ethernet / sata lvcmos clock generator 1 2 3 4 vdd gnd fs 8 7 6 5 clk xtal_in xtal_out vdda oe 15-0106
2 www.pericom.com pi6lc48c51 rev . a 08/27/15 pinout table pin no. pin name i/o ty pe description 1 vdda power analog power supply 2 oe input pull-up high: output enabled; low: output high impedence 3, 4 xtal_out, xtal_in crystal crystal input and output 5 fs input pull-down output frequency select 6 gnd power ground 7 clk output output clock 8 vdd power power supply output frequency table fs crystal frequency (mhz) output frequency (mhz) 0 20.141601 161.132812 1 80.566406 0 19.53125 156.25 1 78.125 0 19.44 155.52 1 77.76 0 18.75 150 1 75 typical crystal requirement parameter minimum ty pica l maximum units mode of oscillation fundamental frequency 17.5 21.25 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive level 1 mw recomended crystal specifcation pericom recommends: a) flxxxx, smd 3.2x2.5(4p), xxxmhz, cl=18pf, +/-20ppm http://www.pericom.com/pdf/datasheets/se/fl.pdf b) b) fyxxxxx, smd 5x3.2(4p), xxxmhz, cl=18pf, +/-30ppm http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
3 www.pericom.com pi6lc48c51 rev . a 08/27/15 maximum ratings (over operating free-air temperature range) ote stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc 3.3v analog supply voltage ...................................... -0.5 to +3.6v esd protection (hbm) ......................................................... 2000v dc electrical characteristics (v dd = v dda , t a = -40 to 85oc) symbol parameter condition min ty p max units v dd, v dda core, analog supply voltage 3.135 3.3 3.465 v v dd, v dda core, analog supply voltage 2.375 2.5 2.625 v i dd power supply current 45 ma i dda analog supply current 30 ma dc electrical characteristics, (v dd = v dda , t a = -40 to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3v 5% 2 v dd +0.3 v v dd = 2.5v 5% 1.7 v dd +0.3 v il input low voltage v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v oh output high voltage v dd = 3.3v 5%, i oh = - 8ma 2.6 v v dd = 2.5v 5%, i oh = - 4ma 90% vdd v ol output low voltage v dd = 3.3v 5%, i ol = 8ma 0.4 v v dd = 3.3v 5%, i ol = 4ma 10% vdd i ih input high current oe, fs v dd = v in = 3.465v 5, 150 ua i il input low current oe, fs v dd = 3.465v, v in = 0v -150,-5 ua pin characteristics c jn input capacitance 4 pf r pullup pull up resistor 51 k r pulldown pull down resistor 51 k r out output impedence 15 pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
4 www.pericom.com pi6lc48c51 rev . a 08/27/15 ac electrical characteristics, (v dd = v dda , t a = -40 to 85oc) symbol parameter condition min. ty p. max units f out output frequency 70 170 mhz t jit(?) rms phase jitter, (random) (1) 155.52mhz, (1.875mhz - 20mhz) 0.2 ps 77.76mhz , (1.875mhz - 20mhz) 0.25 ps t r / t f output rise/fall time 20% to 80% 200 800 ps o dc output duty cycle 48 52 % note: 1. please refer to the phase noise plots. pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
5 www.pericom.com pi6lc48c51 rev . a 08/27/15 50 z = 50 [+v dd /2] [+v dd /2] v dd v dda gnd [-v dd /2] scope lvcmos test circuit power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6lc48c51 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. v dd 0.1f 0.1f 10f 10? * 3.3v or 2.5v v dda * if v dd is 2.5v, the resistor value will be di erent, see app note for details pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
6 www.pericom.com pi6lc48c51 rev . a 08/27/15 crystal input interface te clock generator has been characterized with 18pf parallel resonant crystals. te capacitor values shown in the fgure below were determined using a 17.5~21.25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 33pf c2 22pf xtal_in xtal_out x1 18pf parallel crystal lvcmos to xtal interface te xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in the fgure below. te xtal_out pin can be lef foating. te input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. tis confguration requires that the output impedance of the driver (ro) plus the series resis - tance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. tis can be done in one of the two ways. first, r1 and r2 in parallel should equal the transmission line empedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50. by overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. v r2 50 dd ro rs zo = ro + rs r1 xtal_in xtal_out v dd 0.1f pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
7 www.pericom.com pi6lc48c51 rev . a 08/27/15 ordering information ordering code packaging ty pe package description operating temperature PI6LC48C51LIE l pb-free & green, 8-pin tssop industrial PI6LC48C51LIEx l pb-free & green, 8-pin tssop, tape & reel industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 8-contact tssop (l) date: 05/03/12 description: 8 pin, 173mil wide tssop package code: l document control #: pd-1308 revision: f notes: 1. refer jedec mo-153f/aa 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0370 pi6lc48c51 ethernet / sata lvcmos clock generator 15-0106
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